The present invention relates to the packaging of semiconductor devices, and more particularly to a system and method for interconnecting integrated circuits (ICs) on a semiconductor substrate.
Electronic systems typically are manufactured from two or more ICs to provide complete system function. Until recently the limitations on performance and number of I/O pins were not significant for the vast majority of applications. However, as more devices are integrated in a single IC and as clock speeds increase, limitations on performance and number of I/O pins would be of paramount concern to semiconductor manufacturers. This is because the overall performance of the system is based on multiple ICs is a function of the performance of the individual ICs and of the performance of the signals between the ICs. The performance of the signals between the ICs is in turn a function of the number of signals and the electrical characteristics of the means used to connect the I/O pins of the ICs. A more efficient means for interconnecting ICs is, therefore, becoming an important influence on the cost, size, performance, weight, and efficiency of electronic systems.
Currently, the most common method used for interconnecting ICs is to first package the individual ICs, and then mount the packaged ICs on a substrate such as a printed circuit board. The size of the package is typically several times larger than the IC and is often manufactured from a metal lead frame and protected within a plastic molded case. The packaged ICs are then placed and soldered to a printed circuit board to create a complete electronic system. The advantages of the current method include low cost and protection of the IC during subsequent handling. In addition, the package acts as a standardized carrier for testing of the IC, such that design changes to the printed circuit board may be made cheaply and quickly. Assembly of the IC to the printed circuit board may further be automated. Finally, the current system allows rework of the printed circuit.
A more efficient method of interconnecting ICs has been demonstrated with the use of flip-chip technology in which a silicon substrate having metallization is connected to an integrated circuit via solder connections. This type of coupling between the integrated circuit and the substrate allows increasing the number of I/O pins, compared to other interconnect technology. A drawback with traditional flip-chip technologies concerns the degradation of the electrical connections subsequent to repeated thermal cycling.
What is needed, therefore, is a mounting technique for integrated circuits that facilitates increased I/Os while avoiding thermal degradation of the I/C substrate interface.